:: Sequence Power-aware SoC Design Flow :: Solutions for ESL Power analysis with interface for ESL simulation & ESL synthesis,Low Power Design & Power Analysis,Clock power & clock-gating aware power estimation,High accuracy dynamic voltage drop analysis,IR-drop,Electro Migration,Timing & SIgnal Integrity analysis,Voltage aware timing & SIgnal Integrity analysis,Concurrent analysis of Electro Migration, voltage drop, timing & SIgnal Integrity,MTCMOS power gating,Decoupling cap insertion based on dynamic voltage drop,MTCMOS power gating optimization,Dynamic & leakage power optimization (multi-Vt libraries),Decoupling cap opt & hot-spot spreading,Timing & Signal Integrity optimization,Hierarchical top level optimization and RLC Extraction for Nanometer SoC Design

Sequence Power-Aware Soc Design For Power (DFP) Flow

Sequence is the EDA leader Enabling Design For Power (DFP) with a complete solution for power analysis, reduction and sign-off – early and throughout the design flow. Sequence has fortified its leadership in RTL power with the unveiling of exciting new automatic power reduction in addition to advanced stimulus management for power, power regressions as well as ESL integration. During physical design, Sequence products assure power grid integrity for digital and full-custom designs and reduce leakage power preserving signal integrity. Sequence products are seamlessly integrated at each stage of user's existing design and implementation flow from system level to final sign-off. Sequence’s unique Design For Power (DFP) solution gives customers the competitive advantage necessary to excel in aggressive technology markets.

Sequence Cool by Design Flow: Complementary to Cadence, Synopsys and Magma

Sequence Design For Power flow: Complementary to Cadence, Mentor, Synopsys and Magma

Analysis-driven Automatic RTL Power Reduction

(New) PowerArtist-XP is a complete RTL Design For Power™ platform with fully-integrated advanced analysis and automatic reduction delivering 10% to 60% or more power savings. Comprehensive and automatic RTL power reduction is not just sequential and combinational clock gating, but is also targeted for memory and datapath portions of complex IPs and System-on-Chip (SOC) designs. The analysis-driven reduction approach, combined with a powerful yet intuitive user interface, selects and prioritizes power reduction opportunities for maximizing power savings in minimum time. PowerArtist-XP’s Visualize-Analyze-Reduce framework delivers predictable power reduction while minimizing impact on area, timing, functional ECO complexity and eliminating unnecessary iterations with downstream tools.

Industry-Leading RTL Power Analysis

PowerTheater™ is the de-facto industry standard for RTL power analysis with more than a 100 customers and more than a 1000 tapeouts. With the most comprehensive features for power analysis, PowerTheater enables you to quickly discover power bugs in your designs, manage stimulus for peak and average power, generate custom reports for power regressions using the Open Access database, and more. PowerTheater continues to deliver accuracy early in the design flow with new timing-aware algorithms. PowerTheater tightly integrates with ESL synthesis tools and also provides sign-off gate-level power analysis thereby enabling designers to address power early and track throughout the design flow.

Electrical Integrity Analysis for Nanometer SoC Design

CoolTime™ is the industry's leading cell-based electrical integrity solution for concurrent analysis of voltage drop, power, electromigration (EM), timing and signal integrity (SI) for nanometer SoC designs. Eliminating the need for multiple point tools and iterations, CoolTime renders accurate and convergent analysis of interdependent electrical effects. CoolTime shares a common platform with CoolPower™ optimization to ensure rapid design closure for dynamic voltage drop, leakage power, EM, timing and SI effects.

Power Integrity Closure for Nanometer SoC Designs

CoolPower™ is the industry's leading cell-based Power Integrity solution for concurrent optimization of power, dynamic voltage drop, timing and signal integrity (SI) for nanometer SoC designs. CoolPower predicts and corrects design closure issues both before and after routing. It gives users the ability to interactively optimize hierarchical, multi-million gate SoC designs at the block-level as well as full-chip level. CoolPower integrates into popular third-party place and route tools to enable existing physical flows to reach fast, predictable design closure in silicon geometries below 65 nanometers (nm).

Columbus - RLC Extraction for Nanometer SoC Design

The Columbus™ product suite provides unparalleled RLC parasitic extraction accuracy and versatility to meet the design challenges at 65nm and beyond. Eliminate costly re-spins and tape out your designs with confidence knowing that interconnect parasitics won't compromise performance. Only Columbus's patented extraction engine delivers the precision needed to model on-chip variations in today's advanced process technologies, allowing you to reduce guardbands and achieve silicon success. Columbus offers both gate-level and device-level extraction capabilities, ensuring integration into your power, reliability and signal integrity flows for standard cell, custom digital, mixed signal and analog designs.

COLLATERAL

Design For Power: Sequence Power-aware SoC Design Flow

In the News

Power verification: trust but verify, or verify and trust?
eetimes.com
July 13, 2009

Too Much of a Good Thing?
chipdesignmag.com
May, 2009

Power-Aware Design -- Time To Move Beyond Formats
cadence.com
May 04, 2009

Low-Power Standards War
chipdesignmag.com
March 13, 2009

Best practices for IC power-aware design
scdsource.com
January 13, 2009

Technical Paper

Understanding RTL power reduction techniques
scdsource.com

ESL Synthesis + Power Analysis = Optimal Micro-Architecture
chipdesignmag.com

Gain Abstraction And Accuracy From RTL Power Estimation
Electronic Design