SANTA CLARA, Calif. - Oct. 21, 2008 - Sequence Design's PowerTheater has added new "timing-aware" RTL power analysis features to meet the twin challenges of shrinking process geometries and high-performance devices driving hundreds of clock domains. These changes result in highly accurate, timing-aware RTL power analysis in addition to the 10X productivity boost that RTL power management provides over gate-level.

Sequence's RTL power analysis now takes into consideration clock domain frequencies to even more closely predict synthesized results. Additionally, RTL designers can perform "what-if" performance power analysis utilizing newly added micro-architectures for arithmetic operators. PowerArtist RTL power reduction, with the unique capability to quantify power savings at RTL before any RTL edits are made, benefits directly by utilizing the same power calculation engine as PowerTheater.

"This is the next step in the evolution of RTL design," said Sequence president and CEO Vic Kulkarni. "By using our low-power physical design knowledge to model complex physical effects at RTL, the resulting improvements in accuracy and performance make the pairing of PowerTheater analysis with PowerArtist reduction the 'killer combo' for low-power design."

The RTL power accuracy enhancements will apply across the broad spectrum of design applications supporting hundreds of clock domains with widely ranging frequencies.

About PowerTheater/PowerArtist
PowerTheater is the industry's first RTL power analysis and power prototyping solution with the singular ability to accurately analyze power at RTL and support power management techniques such as voltage islands, mixed voltage threshold, power gating, and clock gating. PowerTheater is used by over 100 customers worldwide including 70 percent of the world's Top 20 largest semiconductor companies.

Built upon the foundation of proven Sequence RTL DFP (Design For Power™) accurate power analysis technology, and Open Access Database, PowerArtist focuses on trimming power in three key areas: Clock, Memory, and Datapath at RTL where designers have maximum opportunities for power reduction. The power savings achieved through these comprehensive techniques are over and above those achieved during synthesis. Next-generation engines examine the RTL code, prioritize power reductions, and either maximize power savings automatically or guide the user through manual edits within a powerful graphical environment, called PowerCanvas™.
For more information: http://www.sequencedesign.com/solutions/overview.php.