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 The
Company |
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 Market |
Sequence
Design, Inc. is in a high-growth arena within the Electronic
Design Automation (EDA) market which is estimated to be $5B
in 2007 according to industry analysts. EDA tools enable designers
of complex semiconductor chips to achieve their design and
implementation goals and meet time to market needs. Low power
is the primary emerging competitive advantage for most designs.
Sequence is in the Top 10 private EDA companies
according to industry sources, of about 280 private companies
addressing the complex system-on-a-chip (SoC) design flow
today.
Sequence tools are used by designers in wireless,
graphics, mobile-computing, networking and ASIC markets. |
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Mission |
Sequence's
mission is to deliver a unique competitive advantage to sub-90
nm System-on-a-Chip (SoC) designers: a design-for
-power (DFP) flow from RTL to sign-off. |
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Customers |
The
Company has over 150 customers worldwide including world's
top semiconductor companies such as NEC, Renesas, NVIDIA,
Qualcomm, Texas Instruments, Samsung, Toshiba, FreeScale,
Matsushita, LG Electronics, AMD and many others. Company's
low-power flow has been adopted and certified by Dongbu HiTek
(Korea) and STARC (Japan).
There are over 275 installed licenses of the front-end products,
PowerTheater, and over 200 licenses of CoolProducts and Columbus
installed on the physical implementation side. The Company
estimates over 1,000 tape-outs by designers and over 200 implementation
tape-outs. |
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The
Solution |
Sequence
Design-for-Power (DFP)™ flow encompasses a
complete solution from micro-architecture and RTL through
gate-level implementation.
During design, Sequence DFP flow offers 3 advantages: |
- Early power analysis, at RTL, before it is too late
to design proactively for power.
- A portfolio of power reduction and power debug solutions
available at RTL, that have been shown to reduce power
from 25% to 50%.
- Qualification of vectors for package selection and
power grid design.
- Products:
- PowerArtist: Automated RTL power reduction with
a comprehensive debug and visualization environment
for RTL power management
- PowerTheater-65: RTL analysis.
- PowerTheater-Explorer: Cockpit and visualization
environment for power reduction.
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During
physical implementation, Sequence solves 3 main issues in
power-aware SoC designs: |
- Accelerated predictable power closure of large, (~900M
transistors including memories and IP) high-performance
designs with over 33% advantage in time to market.
- Ensuring power grid integrity with a comprehensive set
of technologies.
- 20 - 40% power reduction capability which preserves
timing and signal integrity (SI) with time-to-market savings
of 7-10 days per SoC block.
- Products:
- CoolTime: Dynamic and static voltage-drop and electro-migration
(EM) analysis for power grid design.
- CoolCheck: Vectorless, formal power-grid verification.
- CoolPower: Power reduction and optimization concurrent
with timing and signalintegrity optimization.
- Columbus-AMS: Foundation extraction technology which
provides highly accurate 3-D, RLC-interconnect modeling
for both full custom and SoC designs.
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Sequence
tools fit seamlessly with all major vendor flows, including
Cadence, Synopsys and Magma. |
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